The present invention relates to a clock signal generating device or apparatus for generating a clock signal for chopping the duration represented by each of a plurality of time signals, to convert the durations to digital data. The device can be used, e.g., for reading out image data from charge-storage-type image sensors.
For converting the duration of various events to digital data, it is convenient to chop the duration with a clock signal of appropriate frequency and to count the number of repetitions of chopping. In this well-known technique, a time signal which represents the duration of an event is used. It is convenient to represent the duration of an event by a period of time during which the time signal maintains a logic state "HIGH" or "LOW". In converting the duration to time data, the frequency of the clock signal for chopping the duration should be selected. When there are several events, it is recommended to select an appropriate time period from the durations of the events and to determine the clock signal frequency based on the selected time period. FIG. 4 is a circuit block diagram of a prior-art clock signal generating device as disclosed in Japanese Patent Document No. H01-119118.
In FIG. 4, an OR-gate 20 receives a plurality of time signals TS. The time signals TS indicate with a logic state "LOW" the durations of simultaneous events. The OR-gate 20 outputs a reference signal Sr of "HIGH" at a time corresponding to the shortest of the durations. A frequency divider 30 receives a reference clock signal .phi. and outputs a divided clock signal .phi..sub.n the frequency of which is 1/N times the reference clock signal frequency. In the following, N is referred to as "frequency dividing parameter" and 1/N as "frequency dividing ratio".
The frequency dividing ratio 1/N is set at a value suitable for finding as accurately as possible a reference time period for the durations of the simultaneous events. The divided clock signal .phi..sub.N is fed to a counter 40 via an OR-gate 41 which also receives the reference signal Sr output from the OR-gate 20. The OR-gate 41 is enabled by "LOW" of the signal Sr, until the signal Sr turns to "HIGH". Thus, the counter 40 is reset as soon as an event occurs, and starts counting the divided clock signal .phi..sub.N. The counter 40 stops counting the divided clock signal .phi..sub.N when the OR-gate 41 is disabled by "HIGH" of the reference signal Sr. The duration from the start of the event until the generation of the reference signal Sr is denoted by SNT, with a count value S of the counter 40 at the time of its stopping and a period T of the reference clock signal .phi.. The duration SNT is used as a reference time Tr for measuring the duration of a plurality of events.
An output counter 50 is a programmable counter for outputting an output clock signal .phi..sub.O. The output counter 50 starts receiving the reference clock signal .phi. via an AND-gate 51 as soon as the reference signal Sr is generated (i.e., as soon as the reference signal Sr turns to "HIGH") and outputs from its last stage the output clock signal .phi..sub.O as a carry via an OR-gate 52. Since the output of the OR-gate 20 is "LOW" before the reference signal Sr is generated, the OR-gate 52 receives a "HIGH" signal from an inverter 21 and outputs a "HIGH" signal to a program input port PR of the output counter 50. Thus, the output counter 50 is programmed or initialized at the count value S of the counter 40 as soon as the reference signal Sr is generated. And, at the same time when the reference signal Sr is generated, the AND-gate 51 is enabled by "HIGH" of the reference signal Sr, and the OR-gate 52 is enabled by "LOW" of a complementary signal of the reference signal Sr via the inverter 21.
The output counter 50 then outputs the carry in the form of the output clock signal .phi..sub.O from its last stage via OR-gate 52 when the output counter 50 has received the pulses of the reference clock signal .phi. corresponding to its initial set value S via the OR-gate 51. At the same time, the output counter 50 returns to its program input port PR "HIGH" of the output clock signal .phi..sub.O so as to be initialized again. The output counter 50 repeats the same operation and outputs the output clock signal .phi..sub.O each time the output counter 50 receives the reference clock signal pulses corresponding to its initial set value S. At the initial and the following initialization steps, complementary signals of the output from output stages Q0 to Qn of the counter 40 are input to corresponding data input ports DO to Dn of the output counter 50.
The OR-gate 20 detects the reference time Tr as a measure for the duration of events represented by a plurality of time signals TS, and outputs the reference signal Sr. The output counter 50 outputs the output clock signal .phi..sub.O or chopping the duration of the events at every number of pulses of the reference clock signal .phi. corresponding to the count value S of the counter 40 when the reference signal Sr is generated. The period of the output clock signal .phi..sub.O is the same as that of the reference clock signal .phi. when S is zero. Usually, the period of the output clock signal .phi..sub.O is S+1 times the period of the reference clock signal .phi..
Though the output clock signal .phi..sub.O output at a frequency corresponding to the reference time Tr may be used as is for chopping the time represented by each time signal TS, a clock signal obtained by appropriately dividing the output clock signal .phi..sub.O is usually adopted for chopping the durations. When the period of time represented by the time signal TS varies in a wide range, it is desirable to generate a clock signal whose period varies with elapse of time for chopping the variable durations.
The reference time Tr is determined based on the count value S at the time of generation of the reference signal from the counter 40 which receives the clock signal .phi..sub.O obtained by dividing the reference clock signal .phi.. As a result, a time fraction is dropped for the sake of convenience as the period of the divided clock signal .phi..sub.N is an aliquot part of the reference time Tr. An error caused by this dropping of a fractional part is the larger, the closer the dropped part is to the period of the divided clock signal .phi..sub.N. Since the reference time Tr is expressed as Tr=SNT, with the period T of the reference clock signal .phi. and the frequency dividing parameter N of the divided clock signal .phi..sub.N, the error becomes larger with increasing N, and a relative error becomes larger with a decreasing count value S.
The clock signal for chopping the duration of the events is generated from the output clock signal .phi..sub.O, whose period corresponds to the reference time Tr. As a result, the duration is chopped and digitized by the clock signal with an inappropriate period when the error of the reference time Tr is large. As a result, the accuracy of the digital data is impaired. Although the error may be reduced by setting the dividing parameter N at a small value, a small N-value is not suitable for digitizing durations which vary over a wide range. Since a small count value S may be caused by a short reference time even when the frequency dividing ratio is set properly, an error is inevitable.